1. Field of the Invention
This invention relates in general to a process of fabricating semiconductor integrated circuit devices and, in particular, to a process of fabricating multi-level interconnects for the IC devices. More particularly, this invention relates to a process of fabricating unlanded vias for multi-level interconnects for IC devices.
2. Description of Related Art
As the integration density of semiconductor IC devices increases as a result of technology advancements brought about by refined fabrication resolution, more circuit elements are required to be packed into the same surface area of the device substrate. Supports for circuit elements such as interconnects necessary between MOS transistors of the IC device are also required to be fabricated in the same device substrate. Device configurations with multi-leveled designs utilizing multiple layers of metal to contain these interconnects are therefore developed to incorporate these high-density devices.
Between these multiple layers, electrically insulating material known as intermetal dielectrics are used in these configurations to provide isolation in between the layers. Vias are formed in these inter-metal dielectric layers that can be filled with electrically conductive material to form plugs that provide electrical connection between the interconnects in different metal layers.
Conventional fabrication methods employ the technique of photolithography to form vias in an inter-metal dielectric layer by etching into the dielectric layer covered by pattered photoresist layers. Plugs are formed inside these vias by deposition of selected electrically conductive material into the via holes. FIGS. 1A to 1C depict one such conventional fabrication process for making these plugs which is briefly examined bellow.
First, as is illustrated in FIG. 1A, interconnects 12 formed in the metal layer are covered by an inter-metal dielectric layer 16 that provides electrical insulation from other portions of the device. Though not shown in the drawing, however, circuit elements such as MOS transistors formed in the device substrate may be present directly underneath the interconnects 12, as is appreciable by those skilled in the art. Then, after the formation of the inter-metal dielectric layer 16, a photoresist may be formed over the surface of the dielectric and patterned into the desired configuration. Such patterns expose locations in the photoresist where the vias are to be formed, as is clearly seen in the configuration of the photoresist layer 20 schematically shown in the drawing.
Then, in FIG. 1B, etching procedures such as dry etching can be employed to remove the selected regions of the inter-metal dielectric layer 16, forming the vias 18 in the dielectric 16. In general, the etching in the inter-metal dielectric layer 16 can be a two-stage process. In the main etching stage, the majority of the material thickness of the inter-metal dielectric 16 of the intended vias 18 can be removed by etching, but the bottom of the vias at this stage may have not reached the metal layer 12 yet. In a following over-etching stage, residual material in the inter-metal dielectric layer 16 in the regions of the vias 18 is removed, ensuring that the vias 18 reach the metal layer 12.
After the formation of the vias 18 as illustrated in FIG. 1B, plugs 28 shown in FIG. 1C can be formed by deposition of electrically conductive material in the via holes. An etching-back processing based on dry etching or chemical-mechanical polishing (CMP) can then be performed to finish the plugs 28, and another metal layer 22 can then be formed over the surface of the inter-metal dielectric layer 16 that can be used for the fabrication of another layer of interconnects.
In these conventional methods for forming vias 18, the etching operation in the main and over-etching stages is controlled on a time basis. However, etching timing control based on the estimation of the thickness of the inter-metal dielectric layer 16 can be tricky, with the etching results quite different. For example, typical procedures may need about 60 seconds for the main etching stage while only about 10 for the over-etching.
Since the inter-metal dielectric layer 16 is typically much thicker than other layers in the device, if the etch timing control is not governed well, there may be occasions wherein the vias do not reach to the metal layer 12, as is schematically depicted in the cross-sectional view of FIG. 2. Or, there may be occasions wherein the vias penetrate entirely through the inter-metal dielectric 16 to become short-circuited with the MOS transistor, as in FIG. 3, when they land on the device substrate. This later scenario is possible as the IC devices are required to pack more smaller circuit elements and the processing alignment becomes more difficult. The short-circuiting condition demonstrated in FIG. 3 is a result of misalignment of the via with the interconnect it is supposed to contact.